The present invention relates to a semiconductor integrated circuit device which has a design that facilitates testing the manufacturing state of a wafer to check whether the semiconductor integrated circuit device satisfies a desired circuit performance based on a design standard.
Usually, from the viewpoint of improving the reliability in the operation of a semiconductor integrated circuit device, it is necessary to check a wafer in a manufacturing state of the semiconductor integrated circuit device to check whether the semiconductor integrated circuit device satisfies a desired circuit performance or not. As methods for performing such a test, there is known a method of adding a group of gate circuits (a long delay path) to the semiconductor integrated circuit device and a method of adding a scan path group, constructed based on what is called a design for testability, to the semiconductor integrated circuit device.
FIG. 4 is a diagram that shows a circuit construction of the above gate circuit group. This gate circuit group is constructed to have logic gates such as AND gates and OR gates connected in series of several hundred stages between an input buffer and an output buffer. Such a gate circuit group is located within a semiconductor integrated circuit device at a position where it operates independent of the operation of the circuits that achieve the primary functions of the semiconductor integrated circuit device. A test using this gate circuit group is carried out such that a desired signal is first input into an input terminal (IN), and propagation delay time of this signal is monitored when it is output from an output terminal (OUT). The circuitry is diagnosed based on this propagation delay time.
This test is based on the fact that logic gates (semiconductors) on the same semiconductor integrated circuit device, or the same wafer, have substantially the same characteristics, and therefore, the circuit diagnosis of the gate circuit group can be equivalently applied to the diagnosis of the logic circuits that achieve the primary functions of the semiconductor integrated circuit device.
On the other hand, circuits that constitute a scan path group are designed so that they are built into the logic circuits that achieve the primary functions within the semiconductor integrated circuit device. The performance of the circuitry is diagnosed by verifying an output result corresponding to a predetermined scan signal that is input into the logic circuits (hereinafter to be referred to as a scan test). A multi-stage connection of scan flip-flop circuits is known as a representative example of the circuitry that forms the scan path group.
Generally, within a semiconductor integrated circuit device that has been designed to be built in with a scan path group, that is, within a scan-designed semiconductor integrated circuit device, there are disposed a plurality of scan flip-flops that input or output normal-operation input signals to be input during a normal operation or circuit-diagnosis input signals to be input for carrying out the test, at an input pre-stage and an output post-stage of sequential circuits or combination circuits (hereinafter to be collectively referred to as combination circuits) that achieve the primary functions of the semiconductor integrated circuit device.
The plurality of scan flip-flops disposed at the input pre-stage (hereinafter to be referred to as a flip-flop pre-stage section) are constructed such that, when the normal operation mode has been selected, a plurality of externally-applied normal signals are input in parallel to the flip-flop pre-stage section of the combination circuits, and so that, when the test mode has been selected, circuit diagnosis input signals are delivered in series to the flip-flop pre-stage section.
Similarly, the plurality of scan flip-flops disposed at the output post-stage (hereinafter to be referred to as a flip-flop post-stage section) are constructed such that, when the normal operation mode has been selected, a plurality of signals output from the combination circuits are input in parallel to the post-stage section, and that, when the test mode has been selected, circuit diagnosis input signals that have been delivered in series at the flip-flop pre-stage section are delivered in series to the flip-flop post-stage section.
Based on the above arrangement, during the normal operation mode, the scan path group can execute the primary input and output operations of the combination circuits. During the test mode, the scan path group can sequentially take out the output of the combination circuits obtained from the input of the circuit diagnosis input signals, from a predetermined scan flip-flop at the flip-flop post-stage section. Thus, it is possible to diagnose the combination circuits based on the result of this output.
FIG. 5 is a diagram that shows a circuit construction of the above-described scan flip-flop. This scan flip-flop consists of a selector 101, a first latch 102, a second latch 103, and an inverter G10 for inverting a clock signal T. The selector 101 selectively outputs a normal operation input signal D and a circuit diagnosis input signal SI, according to a mode changeover input signal SMC.
The selector 101 consists of an inverter G111 that inverts the mode changeover input signal SMC, an N-channel transmission gate N111 that receives the mode changeover input signal SMC from a control terminal (a gate) and receives the normal operation input signal D from one contact terminal (a source or a drain), and an N-channel transmission gate N112 that receives the output signal of the inverter G111 at a control terminal (a gate) and receives the circuit diagnosis input signal SI from one contact terminal (a source or a drain). The other contact terminal (a drain or a source) of the N-channel transmission gate N111 and the other contact terminal (a drain or a source) of the N-channel transmission gate N112 are connected with each other. The circuit diagnosis input signal SI or the normal operation input signal D is selectively output from the node between these contact terminals.
The first latch 102 receives the normal operation input signal D or the circuit diagnosis input signal SI output by the selector 101, holds the received signal and transmits it to the second latch 103 at the next stage, according to the clock signal T.
The first latch 102 consists of an N-channel transmission gate N121 that receives the clock signal T from a contact terminal (a gate) and whose one contact terminal (a source or a drain) is connected to an output terminal of the selector 101 as an input terminal of the first latch 102. The first latch 102 also has an N-channel transmission gate N122 that receives the output of the inverter G10 at a control terminal (a gate) and whose one contact terminal (a source or a drain) is connected to the other contact terminal (a drain or a source) of the N-channel transmission gate N121. The first latch 102 also has an inverter G121 whose input terminal is connected to the other contact terminal (a drain or a source) of the N-channel transmission gate N121 and whose output terminal is also an output terminal of the first latch 102. The first latch further has an inverter G122 whose input terminal is connected to the output terminal of the inverter G121 and whose output terminal is connected to the other contact terminal (a drain or a source) of the N-channel transmission gate N122.
The second latch 103 is a circuit that holds and outputs a signal output from the first latch 102 according to the clock signal T. The second latch 103 consists of an N-channel transmission gate N131 that receives the output of the inverter G10 from a control terminal (a gate) and whose one contact terminal (a source or a drain) is connected to an output terminal of the first latch 102 as an input terminal of the second latch 103. The second latch 103 also has an N-channel transmission gate N132 that receives the clock signal T from a control terminal (a gate) and whose one contact terminal (a source or a drain) is connected to the other contact terminal (a drain or a source) of the N-channel transmission gate N131. The second latch 103 also has an inverter G131 whose input terminal is connected to the other contact terminal (a drain or a source) of the N-channel transmission gate N131 and whose output terminal is also an output terminal of the second latch 103, that is, as a terminal for outputting an output signal Q of the scan flip-flop. The second latch 103 further has an inverter G132 whose input terminal is connected to the output terminal of the inverter G131 and whose output terminal is connected to the other contact terminal (a drain or a source) of the N-channel transmission gate N132.
The operation of the scan flip-flop will be now explained. First, when the logic level of the mode changeover input signal SMC is xe2x80x9cL(Low)xe2x80x9d, the N-channel transmission gate N111 is turned OFF and the N-channel transmission gate N112 is turned ON. As a result, the circuit diagnosis input signal SI is selectively output from the selector 101. In other words, the scan flip-flop is in test mode when the mode changeover input signal SMC of the logic level xe2x80x9cLxe2x80x9d is input.
When the logic level of the clock signal T is xe2x80x9cH(High)xe2x80x9d, the N-channel transmission gate N121 in the first latch 102 is turned ON. Therefore, the circuit diagnosis input signal SI output from the selector 101 is input into the inverter G121 through the N-channel transmission gate N121. The control terminal of the N-channel transmission gate N122 is supplied with a xe2x80x9cLxe2x80x9d level signal which is an inverted signal of the clock signal T of the logic level xe2x80x9cHxe2x80x9d. Therefore, the N-channel transmission gate N122 is turned OFF, and the output terminal of the inverter G122 is set to a release state. The output signal of the inverter G122 is not input into the inverter G121. In other words, the first latch 102 transmits an inverted signal of the circuit diagnosis input signal SI to the second latch 103 in the next stage.
Similarly, when the logic level of the clock signal T is xe2x80x9cHxe2x80x9d, in the second latch 103, the control terminal of the N-channel transmission gate N131 is supplied with a xe2x80x9cLxe2x80x9d level signal which is an inverted signal of the clock signal T of the logic level xe2x80x9cHxe2x80x9d. Therefore, the N-channel transmission gate N131 is turned OFF, and the signal output from the first latch 102 is not transmitted to the inverter G131. On the other hand, the control terminal of the N-channel transmission gate N132 is input with the clock signal T of the logic level xe2x80x9cHxe2x80x9d. Therefore, the N-channel transmission gate N132 is turned ON, and the signal output from the inverter G131 is inverted by the inverter G132, and is then recursively input into the inverter G131.
In other words, the second latch 103 holds a signal of the logic level that had been output from the inverter G131 until immediately before the logic level of the clock signal T becomes xe2x80x9cHxe2x80x9d. In this state, the signal of the logic level held by the inverters G131 and G132 of the second latch 103 is output as the output signal Q.
When the logic level of the clock signal T is xe2x80x9cLxe2x80x9d, the N-channel transmission gate N121 in the first latch 102 is turned OFF. Therefore, the circuit diagnosis input signal SI that has been output from the selector 101 is not input into the inverter G121. On the other hand, the control terminal of the N-channel transmission gate N122 is supplied with a xe2x80x9cHxe2x80x9d level signal which is an inverted signal of the clock signal T of the logic level xe2x80x9cLxe2x80x9d. Therefore, the N-channel transmission gate N122 is turned ON, and the signal output from the inverter G121 is inverted by the inverter G122, and is then recursively input into the inverter G121. In other words, the first latch 102 holds the signal of a logic level that had been output from the inverter G121 immediately before the logic level of the clock signal T became xe2x80x9cLxe2x80x9d.
Similarly, when the logic level of the clock signal T is xe2x80x9cLxe2x80x9d, in the second latch 103, the control terminal of the N-channel transmission gate N131 is supplied with a xe2x80x9cHxe2x80x9d level signal which is an inverted signal of the clock signal T of the logic level xe2x80x9cLxe2x80x9d. Therefore, the N-channel transmission gate N131 is turned ON. The signal output from the first latch 102, that is, the signal of the logic level held by the inverters G121 and G122 of the first latch 102, is input into the inverter G131 through the N-channel transmission gate N131.
In the same state, the control terminal of the N-channel transmission gate N132 is input with the clock signal T of the logic level xe2x80x9cLxe2x80x9d, and the N-channel transmission gate N132 is turned OFF. Therefore, the output terminal of the inverter G132 is set to a release state, and its output signal is not input into the inverter G131. In other words, the second latch 103 outputs the inverted signal of the signal output from the first latch 102, as the output signal Q of the scan flip-flop.
As explained above, in the test mode operation of the scan flip-flop, when the clock signal T has a logic level xe2x80x9cLxe2x80x9d, the first latch 102 latches the inverted signal of the circuit diagnosis input signal SI at this point of time and inputs this inverted signal to the second latch 103. When the clock signal T changes to the logic level xe2x80x9cHxe2x80x9d, the second latch 103 latches and outputs the inverted signal of the signal that has been output from the first latch 102 at this point of time. Therefore, the scan flip-flop outputs the circuit diagnosis input signal SI by delaying the output by one cycle time of the clock signal T.
When the mode changeover input signal SMC has a logic level xe2x80x9cHxe2x80x9d and the scan flip-flop is in the normal operation mode, the first latch 102 and the second latch 103 carry out a operation similar to that described above respectively, except that the normal operation input signal D is output from the selector 101 in place of the circuit diagnosis input signal SI. Therefore, this explanation will be omitted.
As explained above, the conventional semiconductor integrated circuit device facilitates the diagnosis of the circuit performance and improves the reliability of the operation, according to the design for facilitating the test based on the addition of the gate circuit group and the introduction of the scan path group such as the scan flip-flops.
However, the gate circuit group and the scan path group have different test objects as explained above. Therefore, when it is desired to carry out both the monitoring of the propagation delay time in the logic gate and the scan test of the combined circuits, it has been necessary to design the semiconductor integrated circuit devices such that the circuits for achieving the monitoring and the scan test are separately built into the semiconductor integrated circuit devices.
In recent years, along with the increase in the levels of functions and increase in the processing speed of the semiconductor integrated circuit devices, there has been a tendency that the combined circuits and other logic circuits built into the semiconductor integrated circuit devices are becoming more complex. Therefore, the addition of the circuits necessary for the test brings about an increase in the scale of the circuits. Further, the increase in the number of electrode terminals (pads) has become unavoidable in order to implement the test.
It is an object of the present invention to provide a semiconductor integrated circuit device which can restrict an increase in the circuit scale and which can achieve both the monitoring of the propagation delay time and the test of functions.
In order to achieve the above object by solving the aforementioned problems, according to the present invention, there is provided a semiconductor integrated circuit device having a selector circuit that selects a normal operation signal to be input into the logic circuit during a normal operation mode and a circuit diagnosis input signal to be input into the logic circuit during a test mode, according to a first-mode changeover input signal, and a latch circuit that has a logic gate for inputting and holding or transmitting one of the normal operation signal and the circuit diagnosis input signal (hereinafter to be referred to as a transmission signal) that has been selected by the selector circuit, and that selectively executes a scan mode for either holding or transmitting the transmission signal according to a clock signal and a long delay path function mode for transmitting the transmission signal irrespective of the clock signal, according to a second-mode changeover input signal. Thus, the latch circuit constructed by the test facilitation design functions as a holder for the scan test and as a long delay path by utilizing the logic gates. As a result, it is possible to selectively execute the two kinds of circuit diagnosis test in one latch circuit.
Further, the latch circuit is equipped with at least one latch that has a logic gate for transmitting or holding the transmission signal, a first controller for transmitting or interrupting the transmission signal according to the clock signal when the second-mode changeover input signal shows the scan test mode and for transmitting the transmission signal to the logic gate when the second-mode changeover input signal shows the long delay path function mode, and a second controller for selectively controlling the transmission or the holding of the transmission signal in the logic gate according to the clock signal. The first controller selects the execution of the scan test or the long delay path function. When the scan test has been selected, the logic gates function as the holder for the scan test. When the long delay path function has been selected, the logic gates function as the long delay path. As a result, it is possible to selectively execute the two kinds of circuit diagnosis test in one latch circuit.
Further, first controller has at least one first transmission gate, and the transmission signal is transmitted to the logic gate through the first transmission gate, and the second controller has at least one second transmission gate, and the logic gate selectively controls the transmission and the holding of the transmission signal in the logic gate by ON/OFF controlling the second transmission gate based on the clock signal. The first controller controls the selection of the transmission of the transmission signal to the logic gate based on the first transmission gate, and the second controller controls the selection of the transmission or the holding of the transmission signal based on the second transmission gate. Therefore, it is possible to select either the scan mode or the long delay path function mode by suitably selecting the logic levels to be given to the first and second transmission gates.
Further, the first and second transmission gates are N-/P-channel transmission gates. N-/P-channel transistor gates are used for controlling the transmission or the holding of the transmission signal in the first controller and the second controller respectively. Therefore, it is possible to achieve a stable and secure transmission of the signal of the logic level xe2x80x9cHxe2x80x9d.
Further, the logic gate has a first inverter for inverting a signal transmitted through the first controller and outputting the inverted signal, a second inverter for inverting a signal output from the first inverter and inputting the inverted signal to the first inverter through the second controller, and a third transmission gate for interrupting an output signal of the second inverter from being input into the first inverter when the second-mode changeover input signal shows the long delay path function mode. When the second-mode changeover input signal shows the long delay path function mode, the third transmission gate interrupts the output signal of the second inverter from being recursively input into the first inverter, where the second inverter becomes valid only when the logic gate functions as the holder, and the first inverter becomes valid both when the logic gate functions as the transmitter and as the holder. Therefore, it is possible to avoid the collision of the signal generated at the input stage of the first inverter by interrupting the second transmission gate from being turned ON during the long delay path function mode.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.